1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a semiconductor device with lowered-parasitic capacitance.
2. Description of the Related Art
Semiconductor devices are structured to be finer with correspondence to the largeness of the scale thereof. The finer the structure is, the stronger the influence of the performance of a semiconductor because of the parasitic resistance and the parasitic capacitance. In order to perform a larger scale of an integrated circuit or improve the speed of the calculation, it is necessary for the larger scale of integrated circuit itself to operate with higher speed.
It is a basic principal that the speed of operation of a semiconductor device depends on the product of the resistance of a semiconductor element as a switching element by the capacitance of the gate thereof, called the CR time constant. The smaller the CR time constant, the higher the speed of operation. The higher performance in speed is improved by the finer structure of a semiconductor device with the smaller CR time constant.
The problem remains in that the performance of a circuit is not more desirably improved in spite of the finer structure because both the parasitic resistance and the parasitic capacitance actually remain in the circuit. In regarding to the parasitic w capacitance, the fringe capacitance formed w between a gate electrode and a source/drain region as a diffusion layer region, is an important issue in the improvement of the performance of a circuit.
One example of the conventional MOSFET-structure is disclosed in Japanese Laid-Open Patent application (JP-A-Heisei 7-193233). In this MOSFET-structure, a air gap is formed for lowering the parasitic capacitance between a gate electrode and a source/drain region. In FIG. 1, in the side portion of an gate electrode 20, a Si.sub.3 N.sub.4 layer (not shown) is provided. Next, a source/drain 30 is formed by injecting ions. After that, a mounting potion is mounted on the source/drain 30 by selective epitaxial method. After the Si.sub.3 N.sub.4 layer is removed, then a CVD oxide layer 70 is deposited such that the removed Si.sub.3 N.sub.4 layer is replaced by a vacuum.
In this structure, the oxide layer 70, with the relative permitivity 3.9, located on the side portion of the gate electrode 20, is removed. As a result, the fringe capacitance between the gate electrode 20 and the source/drain 30 is lowered in comparison with another one wherein the oxide layer 70 is filled therein. Thereby, the parasitic capacitance is lowered.
Also, Togo showed another structure of MOSFET in his paper (1996, Symposium On VLSI Technology, Digest of Technical Papers). In this structure, without using a selective Si-growth method, an air gap as a space is formed around a Si-polycrystaline portion by etching the side wall portion of MOSFET. As shown in FIG. 2A, a gate electrode 5 is formed on a silicon plate 1 through a gate oxide layer 4. After that, a first side wall as a silicon nitride layer 17 is formed on the side surface of the gate electrode 5. In FIG. 2B, a second side wall as a silicon oxide layer 18 is formed on the side surface of the first side wall. Further, in FIG. 2C, the first side wall is removed by etching to form an air gap 11A around the gate electrode 5.
However, in the method shown in FIG. 1, it is necessary to use a selective Si-growth method for a source/drain region. Therefore, the method is complicated. Further, according to current selective Si-growth technology, it is inevitable to generate a great deal of farsets at the end portions of the growth region, if the selectivity is improved with respect to the surfaces of the oxide film and the silicon film layer. Thereby, it has a demerit that it is difficult to form the air gaps. It is desirable that such air gaps are formed so that the fringe capacitance between the gate electrode and the source/drain is decreased without any complicated procedures.
On the other hand, in the method shown in FIG. 2A-2C, it is necessary to etch the narrow gaps formed around the fringe of the Si-polycrystaline gate electrode, that is, the gaps corresponding to the region of high aspect ratio. Therefore, it is very difficult to form the air gaps 11A.
As mentioned above, it is necessary to lower the parasitic capacitance of a circuit in order to improve the performance thereof. Such an improvement may not cause the complication of process for manufacturing circuits and the narrower process window therefor.